1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to an array substrate of a liquid crystal display and a fabricating method thereof that are adaptive for increasing an aperture ratio and a capacitance value of a storage capacitor.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) controls light transmittances of liquid crystal cells in response to a video signal, thereby display image data (picture). An active matrix LCD having a switching device for each liquid crystal cell is suitable for displaying a moving picture. In general, the active matrix LCD uses a thin film transistor (TFT) as the switching device.
The LCD uses a storage capacitor for sustaining a voltage charged in a liquid crystal cell to ensure stability of a gray level display. The storage capacitor may be classified into two categories: a storage-on-gate (SOG) system that overlaps a portion of the (n−1)th gate line with the nth pixel electrode to form a storage capacitor of the nth pixel; and a storage-on-common (SOC) system that provides a separate common electrode at a lower portion of a pixel electrode to form a storage capacitor.
FIG. 1 is a plan view showing a structure of an array substrate of a conventional LCD adopting a storage-on-gate system, and FIG. 2 is a cross sectional view of the array substrate taking along I–I′ in FIG. 1. In FIGS. 1 and 2, a lower substrate 11 of the LCD includes a TFT arranged at an intersection between a gate line 15′ and a data line 17, a pixel electrode 33 connected to a drain electrode 27 of the TFT, and a storage capacitor positioned at an overlapping portion between the pixel electrode 33 and the pre-stage gate line 15.
The TFT includes a gate electrode 13 connected to the gate line 15′, a source electrode 25 connected to the data line 17, and a drain electrode 27 connected, via a first contact hole 30a, to the pixel electrode 33. The TFT further includes a gate insulating film 19 for electrically insulating the gate electrode 13 and the source and drain electrodes 25 and 17, and semiconductor layers 21 and 23 defining a conduction channel between the source electrode 25 and the drain electrode 27 by application of a gate voltage to the gate electrode 13. The TFT responds to a gate signal from the gate line 15′ to selectively apply a data signal from the data line 17 to the pixel electrode 33.
The pixel electrode 33 is positioned at a cell area divided by the data line 17 and the gate line 15′ and is made from a transparent conductive material having a high light transmittance. The pixel electrode 33 is provided on a protective film 31 coated on an entire surface of the lower substrate 11 and is electrically connected, via the first contact hole 30a defined at the protective film 31, to the drain electrode 27. The pixel electrode 33 generates a potential difference from a common transparent electrode (not shown) provided at an upper substrate (not shown) by the data signal applied via the TFT. This potential difference allows a liquid crystal positioned between the lower substrate 11 and the upper substrate (not shown) to change a liquid crystal molecule arrangement owing to its dielectric anisotropy characteristic. Accordingly, an arrangement of the liquid crystal molecules is changed for each pixel in accordance with the data voltage applied via the TFT, thereby displaying image data information on the LCD.
The storage capacitor should have a large capacitance value enough to keep the pixel voltage stable. Accordingly, the storage capacitor includes a capacitor electrode 29 electrically connected, via a second contact hole 30b, to the pixel electrode, and a gate line 15 having the gate insulating film 19 disposed therebetween.
FIGS. 3A to 3E are cross sectional views showing a method of fabricating the array substrate of the LCD shown in FIG. 2.
In FIG. 3A, the gate electrode 13 and the gate line 15 are provided on the substrate 11. The gate electrode 13 and the gate line 15 are formed by depositing aluminum (Al) or copper (Cu) material, using a deposition technique such as a sputtering, and then patterning the material.
In FIG. 3B, a gate insulating film 19, an active layer 21 and an ohmic contact layer 23 are provided on the substrate 11. The gate insulating film 19 is formed by depositing an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) using a plasma enhanced chemical vapor deposition (PECVD) technique to cover the gate electrode 13 and the gate line 15. The active layer 21 and the ohmic contact layer 23 are formed by sequentially depositing two semiconductor layers on the gate insulating film 19 and patterning the deposited semiconductor layers. The active layer 21 is formed from amorphous silicon that is not doped with an impurity, and the ohmic contact layer 23 is formed from amorphous silicon doped with an n-type or p-type impurity at a high concentration.
In FIG. 3C, a data line 17 (in FIG. 1), the source and drain electrodes 25 and 27 and the capacitor electrode 29 are provided on the gate insulating film 19 by depositing a metal layer using a CVD or sputtering technique and patterning. After the source and drain electrodes 25 and 27 are patterned, the ohmic contact layer 23 at an area corresponding to the gate electrode 13 is patterned to expose the active layer 21. The area of the active layer 21 corresponding to the gate electrode 13 between the source and drain electrodes 25 and 27 provides a channel. The capacitor electrode 29 overlaps with the gate line 15. The data line 17 (in FIG. 1), the source and drain electrodes 25 and 27, and the capacitor electrode 29 are made from chrome (Cr) or molybdenum (Mo) material.
In FIG. 3D, a protective film 31 having first and second contact holes 30a and 30b is provided. The protective layer 31 is formed by depositing an insulating material on the gate insulating layer 19 and patterning the material to cover the source and drain electrodes 25 and 27. The protective film 31 is made from an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx).
In FIG. 3E, a pixel electrode 33 is provided on the protective film 31. The pixel electrode 33 is formed by depositing a transparent conductive material on the protective film 31 and then patterning the material. The pixel electrode 33 is electrically connected, via the first contact hole 30a, to the drain electrode 27 and is electrically connected, via the second contact hole 30b, to the capacitor electrode 29. The pixel electrode 33 is made from a transparent conductive material such as indium-tin-oxide (ITO), indium-zinc-oxide (IZO) or indium-tin-zinc-oxide (ITZO).
FIG. 4 is a plan view showing a structure of an array substrate of a conventional LCD adopting a storage-on-common system, and FIG. 5 is a cross sectional view of the array substrate taking along II–II′ in FIG. 4. In FIG. 4, a storage capacitor 50 is positioned at center portion of a pixel area. The storage capacitor 50 should have a capacitance value large enough to keep a pixel voltage stable. Accordingly, the storage capacitor 50 includes a pixel electrode 55 electrically connected to a drain electrode 59, and a capacitor common electrode 45 having a gate insulating film 49 disposed therebetween.
FIGS. 6A to 6D are cross sectional views showing a method of fabricating the array substrate of the LCD shown in FIG. 5.
In FIG. 6A, a gate electrode 43, a capacitor electrode 45, and a gate line 47 are provided on the substrate 41 by depositing aluminum (Al) or copper (Cu) material using a deposition technique such as a sputtering and then patterning the material.
In FIG. 6B, a gate insulating film 49, an active layer 51, and an ohmic contact layer 53 are provided on the substrate 41. The gate insulating film 49 is formed by depositing an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) using a plasma enhanced chemical vapor deposition (PECVD) technique to cover the gate electrode 43, the capacitor common electrode 45, and the gate line 47. The active layer 51 and the ohmic contact layer 53 are formed by sequentially depositing two semiconductor layers on the gate insulating film 49 and then patterning the disposed semiconductor layers. The active layer 51 is formed from amorphous silicon that is not doped with an impurity, and the ohmic contact layer 53 is formed from amorphous silicon doped with an n-type or p-type impurity at a high concentration.
In FIG. 6C, a pixel electrode 55, a data line 63, and source and drain electrodes 57 and 59 are provided on the gate insulating film 49. The pixel electrode 55 is formed by depositing a transparent conductive material on the gate insulating film 49 and then patterning the material. The pixel electrode 55 is made from any one of ITO, IZO and ITZO. Subsequently, the data line 63, and the source and drain electrodes 57 and 59 are provided. The data line 63, and the source and drain electrodes 57 and 59 are formed by depositing a metal layer using a CVD or sputtering technique, and then patterning the metal layer. After the source and drain electrodes 57 and 59 are patterned, the ohmic contact layer 53 is patterned at an area corresponding to the gate electrode 43 to expose the active layer 51. The area of the active layer 51 corresponding to the gate electrode 43 between the source and drain electrodes 57 and 59 provides a channel. The drain electrode 59 electrically contacts the pixel electrode 55 without any contact hole. The data line 63 and the source and drain electrodes 57 and 59 are made from chrome (Cr) or molybdenum (Mo).
In FIG. 6D, a protective film 61 is provided at a TFT area. The protective film 61 is formed by depositing an insulating material on the gate insulating layer 19, and then patterning the material to cover the source and drain electrodes 57 and 59. The protective film 61 is made from an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx).
To overcome a flicker phenomenon, the capacitance of the storage capacitor is increased by increasing an area of the capacitor electrode. Accordingly, in a storage-on-gate system, a width of the gate line is increased to increase the capacitance of the storage capacitor. However, since an aperture ratio is reduced, and a line delay effect of a gate signal is enhanced when a width of the gate line is widened, there is a limit in widening the gate line. Furthermore, since the LCD of a storage-on-common system has the storage capacitor provided at a center of the pixel cell, the aperture ratio is reduced more than the LCD of a storage-on-gate system. As previously described, as an area of the capacitor electrode is increased, aperture ratio is reduced. In particular, high pixel density, ferroelectric, and semi-ferroelectric LCD's require high capacitance storage capacitors and high aperture ratios.